Intro to Computer Systems

Chapter 5: Memory & Hamming/SECDED Codes

Memory Addressing

In high-level circumstances, such as when writing a program in a high-level programming language, memory addressing is a simple flat file of addresses which can be allocated and used at will.

However, in reality it is very unlikely that this is the case. Memory controller hardware, and the operating system that provides the interface between application software and the hardware, translate these simple high-level memory operations into what is really involved in managing the memory.

Memory Addressing in Hardware

In the software world, pages can be of variable size as there are no physical limitations outside the addressing range of the hardware it's running on - and with modern 64-bit systems this is no longer an issue. In the hardware world, however, the world is very different: there isn't just "one" memory chip, there are dozens that work together to build the total amount of memory in the system.

Something has to translate this flat-file software world to the discrete chips of the hardware world, and this is the job of the memory controller, a part of the CPU. It is aware of the memory chips under its management, and distributes the address space across them.

Hardware Memory Access

Memory chips themselves aren't a flat file - they are a two-dimensional matrix that is arranged into rows and columns. When a memory address is requested, the memory controller needs to:

Accessing the row and column of the memory chip takes some time. This is a significant contributor to memory latency - how long it takes to get the data out of a particular memory area.

It is typical for quality memory modules to have not only their memory clock speed written on the label, but also its latency with a series of numbers. For example:

A sticker from a DDR3 memory module. Photo:
A sticker from a DDR3 memory module. Photo:

This DDR3 memory module has a series of timing information. They are typically of the form:

DDRx-yyyy CLa-b-c-d

Four more data points follow: have a more in-depth guide to understanding RAM timings, and these performance metrics.

The reason why it takes a while for these processes to take place is due to internal propagation delays within the memory chip itself: not every step to complete each task can (or will) take exactly the same time. These figures specify how long the manufacturer rates the chip to complete these operations, in a stable manner.

Fortunately, most of this complication is hidden from the hardware technician: the memory module will have a piece of "Serial Presence Detect" data, from which the system can fetch these rated timings so that the memory can be configured automatically.

Hardware 'tweakers' (those who have a hobby of getting maximum performance out of their systems) will often push the memory chips over the rated stable timings, in the hope of squeezing extra performance.

Multi-Channel Memory

One way of minimising memory latency (and as such, improving performance) is to interleave the memory requests over multiple channels. That is, instead of relying on a single bank of memory for accessing data, these operations are distributed over a number of memory banks, and the instructions split between them.

Memory interleaving is the technique behind multi-channel memory architecture (e.g. "dual channel") in modern computer systems.

For example, all odd-numbered memory addresses are stored in one bank of memory (bank A), and even-numbered address stored in another (bank B). Then, when a block of memory is accessed, each memory access instruction is split between the two banks, significantly reducing the effective latency of the memory operation as a whole.